| PART |
Description |
Maker |
| ACTS74HMSR-02 |
Dual D Type Flip Flop with Set and Reset, Advanced Logic, CMOS; Temperature Range: -55°C to 125°C; Package: Die (Military Visual) ACT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC14
|
Intersil, Corp.
|
| MC10H106 MC100EL29DWR2 MC10H117 MC10H117FN MC100EP |
Triple 4-3-3-Input NOR Gate
5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset
Dual 2-Wide 2-3-Input OR-AND/OR-AND-Invert Gate
3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing
5V ECL 2-Input XOR/XNOR
4-Wide OR-AND/OR-ANDbar Gate
5V ECL 1:2 Differential Fanout Buffer
3.3V / 5V ECL 6-Bit Differential Register with Master Reset
3.3V ECL Triple D-Type Flip-Flop with Set and Reset
3.3V / 5V ECL ÷2 Divider
5V ECL Differential Data and Clock D Flip-Flop
|
ON Semiconductor
|
| 74LVC74ABQ-Q100 74LVC74AD-Q100 74LVC74APW-Q100 |
Dual D-type flip-flop with set and reset; positive-edge trigger
|
NXP Semiconductors
|
| MC74VHCT74A06 MC74VHCU04DR2G MC74VHCU04DR2 MC74VHC |
Hex Inverter (Unbuffered)
Dual D?Type Flip?Flop with Set and Reset
|
ONSEMI[ON Semiconductor]
|
| 74ALVC74PW 74ALVC74 74ALVC74BQ 74ALVC74D |
Dual D-type flip-flop with set and reset; positive-edge trigger 带设置和复位功能的双D触发器；上升沿触
|
NXP Semiconductors N.V.
|
| 74VHC74MTC 74VHC74N 74VHC74SJ 74VHC74 74VHC74MTCX |
Dual D-Type Flip-Flop 双D型触发器
Supervisor Push-Pull Active High, -40C to 85C, 3-SOT-23, T/R
Dual D-Type Flip-Flop with Preset and Clear
|
Fairchild Semiconductor, Corp.
|
| 74AHC74D118 74AHCT74D 74AHC74PW-T 74AHCT74D-T 74AH |
Dual D-type flip-flop with set and reset; positive-edge trigger
Dual D-type flip-flop with set and reset; positive-edge trigger
|
NXP Semiconductors N.V.
|
| 74HCT74N 74HCT74BQ 74HCT74D 74HCT74DB 74HC74 74HCT |
Dual D-type flip-flop with set and reset; positive edge-trigger
Dual D-type flip-flop with set and reset; positive edge-trigger
|
NXP Semiconductors
|
| 74LV109 74LV109D 74LV109DB 74LV109N 74LV109PW 74LV |
Dual JK flip-flop with set and reset; positive-edge trigger LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
From old datasheet system
|
NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
|
| 74AUP1G74GT-G 74AUP1G74GF |
Low-power D-type flip-flop with set and reset; positive-edge trigger AUP/ULP/V SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8
|
NXP Semiconductors N.V.
|
| 74AUP1G74GD 74AUP1G74GM125 |
Low-power D-type flip-flop with set and reset; positive-edge trigger
Low-power D-type flip-flop with set and reset; positive-edge trigger; Package: SOT902-1 (XQFN8U); Container: Reel Pack, Reverse, Reverse
|
NXP Semiconductors
|
